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<title>PMULLW—Multiply Packed Signed Integers and Store Low Result </title></head>
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<h1>PMULLW—Multiply Packed Signed Integers and Store Low Result</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F D5 /<em>r</em><sup>1</sup></p>
<p>PMULLW <em>mm, mm/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Multiply the packed signed word integers in <em>mm1</em> register and <em>mm2/m64</em>, and store the low 16 bits of the results in <em>mm1</em>.</td></tr>
<tr>
<td>
<p>66 0F D5 /<em>r</em></p>
<p>PMULLW <em>xmm1</em>, <em>xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Multiply the packed signed word integers in <em>xmm1</em> and <em>xmm2/m128</em>, and store the low 16 bits of the results in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG D5 /r</p>
<p>VPMULLW <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Multiply the packed dword signed integers in <em>xmm2</em> and <em>xmm3/m128</em> and store the low 32 bits of each product in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG D5 /r</p>
<p>VPMULLW <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Multiply the packed signed word integers in <em>ymm2</em> and <em>ymm3/m256</em>, and store the low 16 bits of the results in <em>ymm1</em>.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG D5 /r</p>
<p>VPMULLW xmm1 {k1}{z}, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Multiply the packed signed word integers in xmm2 and xmm3/m128, and store the low 16 bits of the results in xmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG D5 /r</p>
<p>VPMULLW ymm1 {k1}{z}, ymm2, ymm3/m256</p>
<p>EVEX.NDS.512.66.0F.WIG D5 /r</p>
<p>VPMULLW zmm1 {k1}{z}, zmm2, zmm3/m512</p></td>
<td>
<p>FVM</p>
<p>FVM</p></td>
<td>
<p>V/V</p>
<p>V/V</p></td>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p>
<p>AVX512BW Multiply the packed signed word integers in</p></td>
<td>
<p>Multiply the packed signed word integers in ymm2 and ymm3/m256, and store the low 16 bits of the results in ymm1 under writemask k1.</p>
<p>zmm2 and zmm3/m512, and store the low 16 bits of the results in zmm1 under writemask k1.</p></td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destina-tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)</p>
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-tion register remain unchanged.</p>
<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.</p>
<p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1.</p>
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<h3>Figure 4-13.  PMULLU Instruction Operation Using 64-bit Operands</h3>
<h2>Operation</h2>
<p><strong>PMULLW (with 64-bit operands)</strong></p>
<pre>    TEMP0[31:0] ←
                         DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
    TEMP1[31:0] ←
                         DEST[31:16] ∗ SRC[31:16];
    TEMP2[31:0] ←
                         DEST[47:32] ∗ SRC[47:32];
    TEMP3[31:0] ←
                         DEST[63:48] ∗ SRC[63:48];
    DEST[15:0] ←
                         TEMP0[15:0];
    DEST[31:16] ←
                         TEMP1[15:0];
    DEST[47:32] ←
                         TEMP2[15:0];
    DEST[63:48] ←
                         TEMP3[15:0];</pre>
<p><strong>PMULLW (with 128-bit operands)</strong></p>
<pre>    TEMP0[31:0] ←
                         DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *)
    TEMP1[31:0] ←
                         DEST[31:16] ∗ SRC[31:16];
    TEMP2[31:0] ←
                         DEST[47:32] ∗ SRC[47:32];
    TEMP3[31:0] ←
                         DEST[63:48] ∗ SRC[63:48];
    TEMP4[31:0] ←
                         DEST[79:64] ∗ SRC[79:64];
    TEMP5[31:0] ←
                         DEST[95:80] ∗ SRC[95:80];
    TEMP6[31:0] ←
                         DEST[111:96] ∗ SRC[111:96];
    TEMP7[31:0] ←
                         DEST[127:112] ∗ SRC[127:112];
    DEST[15:0] ←
                         TEMP0[15:0];
    DEST[31:16] ←
                         TEMP1[15:0];
    DEST[47:32] ←
                         TEMP2[15:0];
    DEST[63:48] ←
                         TEMP3[15:0];
    DEST[79:64] ←
                         TEMP4[15:0];
    DEST[95:80] ←
                         TEMP5[15:0];
    DEST[111:96] ←  TEMP6[15:0];
    DEST[127:112] ← TEMP7[15:0];
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPMULLW (VEX.128 encoded version)</strong></p>
<pre>Temp0[31:0] (cid:197) SRC1[15:0] * SRC2[15:0]
Temp1[31:0] (cid:197) SRC1[31:16] * SRC2[31:16]
Temp2[31:0] (cid:197) SRC1[47:32] * SRC2[47:32]
Temp3[31:0] (cid:197) SRC1[63:48] * SRC2[63:48]
Temp4[31:0] (cid:197) SRC1[79:64] * SRC2[79:64]
Temp5[31:0] (cid:197) SRC1[95:80] * SRC2[95:80]
Temp6[31:0] (cid:197) SRC1[111:96] * SRC2[111:96]
Temp7[31:0] (cid:197) SRC1[127:112] * SRC2[127:112]
DEST[15:0] (cid:197) Temp0[15:0]
DEST[31:16] (cid:197) Temp1[15:0]
DEST[47:32] (cid:197) Temp2[15:0]
DEST[63:48] (cid:197) Temp3[15:0]
DEST[79:64] (cid:197) Temp4[15:0]
DEST[95:80] (cid:197) Temp5[15:0]
DEST[111:96] (cid:197) Temp6[15:0]
DEST[127:112] (cid:197) Temp7[15:0]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>PMULLW (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k1[j] OR *no writemask*
         THEN
              temp[31:0] (cid:197) SRC1[i+15:i] * SRC2[i+15:i]
              DEST[i+15:i] (cid:197) temp[15:0]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+15:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);</p>
<p>VPMULLW __m512i _mm512_mask_mullo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);</p>
<p>VPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);</p>
<p>VPMULLW __m256i _mm256_mask_mullo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);</p>
<p>VPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);</p>
<p>VPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);</p>
<p>PMULLW: __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)</p>
<p>(V)PMULLW: __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)</p>
<p>VPMULLW:__m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded instruction, see Exceptions Type E4.nb.</p></body></html>